The present invention relates to semiconductor devices and control systems, and, for example, to a semiconductor device including a phase locked loop (PLL) circuit that generates a clock signal having a predetermined frequency, and a control system including the semiconductor device.
Some semiconductor devices use a PLL circuit to generate operating clocks having a required frequency from reference clocks having a constant frequency. An example of the PLL circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2010-62707 (Patent literature 1).
The PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2010-62707 includes: a voltage-current converter that converts a voltage into a control current, the voltage being generated in accordance with a phase difference between an input pulse signal and a feedback pulse signal fed back from an output side; a current controlled oscillator that generates a pulse signal having a frequency in accordance with the control current; a current detection unit that detects the control current; and a frequency range switch that switches a frequency range of the output pulse signal, which is output from the current controlled oscillator, in accordance with the detected control current.